Interconnect tree optimization algorithm in nanometer very large scale integration designs

This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very Large Scale Integration (VLSI) layout designs. The algorithm is called Hybrid Routing Tree and Buffer insertion with Look-Ahead (HRTB-LA). In recent VLSI designs, interconnect delay becomes a dominant factor compared to gate delay. The well-known technique to minimize the interconnect delay is by inserting buffers along the interconnect wires. In conventional buffer insertion algorithms, the buffers are inserted on the fixed routing paths. However, in a modern design, there are macro blocks that prohibit any buffer insertion in their respective area. Most of the conventional buffer insertion algorithms do not consider these obstacles. In the presence of buffer obstacles, post routing algorithm may produce poor solution. On the other hand, simultaneous routing and buffer insertion algorithm offers a better solution, but it was proven to be NP-complete. Besides timing performance, power dissipation of the inserted buffers is another metric that needs to be optimized. Research has shown that power dissipation overhead due to buffer insertions is significantly high. In other words, interconnect delay and power dissipation move in opposite directions. Although many methodologies to optimize timing performance with power constraint have been proposed, no algorithm is based on grid graph technique. Hence, the main contribution of this thesis is an efficient algorithm using a hybrid approach for multi-constraint optimization in multi-terminal nets. The algorithm uses dynamic programming to compute the interconnect delay and power dissipation of the inserted buffers incrementally, while an effective runtime is achieved with the aid of novel look-ahead and graph pruning schemes. Experimental results prove that HRTB-LA is able to handle multi-constraint optimizations and produces up to 47% better solution compared to a post routing buffer insertion algorithm in comparable runtime

A secure message handler using microsoft cryptoapi

In this project, a message handler with security features is developed using Microsoft CryptoAPI. The source code is written in Visual Basic to take advantage of the extensive graphical features of the language. A Visual Basic module called clsCiyptoAPI was developed to make calls to the advapi32.dll where the functions for the CryptoAPI reside. This module comprises seven routines, which are; a ByteToArray routine, ConvertByteToHex routine, ConvertStringFromHex routine, ConvertStringtoHex routine, CreateHash routine, CiyptEncrypt routine, and CryptDecrypt routine. These routines were compiled together to form the Dynamic Link Library (DLL) file. This dll file serves as a reference for any Visual Basic application which needs to call the CtyptoAPI function. A simple application is also developed to illustrate how to use this module to develop the user applications. This application demonstrates how to hash, encrypt and decrypt the string and various types of files using several cryptography algorithms provided by the CiyptoAPI function. This project also shows how to use a cryptography technique in network systems

Current THD and Output Voltage Ripple Characteristics of Flyback PFC Converters with LED Lamp and Nonlinear RL Loads

This study analysed the characteristics of total harmonic distortion (THD) and output voltage ripple in a flyback PFC converter circuit under two different loads, which are the LED lamp modules and nonlinear RL loads. The converter was designed to step down the AC input voltage (90 V-265 V) to a DC output voltage of 80 V DC for both loads, each with an output power of 16 W. The main objectives were to observe and assess current THD and output voltage ripple for both loads using two different capacitances of the output capacitor, which are 2400 μF and 6 μF, respectively. The results demonstrated that using smaller capacitors (6 μF), it increased output voltage ripple, which it increased for the LED lamp load from 10% to 25% and for the nonlinear RL load it increased from 15% to 70%. However, with the same smaller capacitors (6 μF), it reduced current THD for both loads, which for the LED lamp load it reduced from 12% to 10.3%, and for the nonlinear RL load it reduced from 13.7% to 8.3%. From these results, with 2400 μF of the output capacitor, it provided better performance in terms of current THD and output voltage ripple for both load types.

Current THD and Output Voltage Ripple Characteristics of Flyback PFC Converters with LED Lamp and Nonlinear RL Loads

This study analysed the characteristics of total harmonic distortion (THD) and output voltage ripple in a flyback PFC converter circuit under two different loads, which are the LED lamp modules and nonlinear RL loads. The converter was designed to step down the AC input voltage (90 V-265 V) to a DC output voltage of 80 V DC for both loads, each with an output power of 16 W. The main objectives were to observe and assess current THD and output voltage ripple for both loads using two different capacitances of the output capacitor, which are 2400 μF and 6 μF, respectively. The results demonstrated that using smaller capacitors (6 μF), it increased output voltage ripple, which it increased for the LED lamp load from 10% to 25% and for the nonlinear RL load it increased from 15% to 70%. However, with the same smaller capacitors (6 μF), it reduced current THD for both loads, which for the LED lamp load it reduced from 12% to 10.3%, and for the nonlinear RL load it reduced from 13.7% to 8.3%. From these results, with 2400 μF of the output capacitor, it provided better performance in terms of current THD and output voltage ripple for both load types.